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CMOS SyncFIFOTM 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
FEATURES:
* * * * * * * * * * * * * * * *
IDT72420 IDT72200 IDT72210 IDT72220 IDT72230 IDT72240
DESCRIPTION:
The IDT72420/72200/72210/72220/72230/72240 SyncFIFOTM are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These devices have a 64, 256, 512, 1,024, 2,048, and 4,096 x 8-bit memory array, respectively. These FIFOs are applicable for a wide variety of data buffering needs, such as graphics, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 8-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and a Write Enable pin (WEN). Data is written into the Synchronous FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and a Read Enable pin (REN). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. An Output Enable pin (OE) is provided on the read port for three-state control of the output. These Synchronous FIFOs have two endpoint flags, Empty (EF) and Full (FF). Two partial flags, Almost-Empty (AE) and Almost-Full (AF), are provided for improved system control. The partial (AE) flags are set to Empty+7 and Full-7 for AE and AF respectively. These FIFOs are fabricated using IDT's high-speed submicron CMOS technology.
64 x 8-bit organization (IDT72420) 256 x 8-bit organization (IDT72200) 512 x 8-bit organization (IDT72210) 1,024 x 8-bit organization (IDT72220) 2,048 x 8-bit organization (IDT72230) 4,096 x 8-bit organization (IDT72240) 10 ns read/write cycle time (IDT72420/72200/72210/72220/72230/ 72240) Read and Write Clocks can be asynchronous or coincidental Dual-Ported zero fall-through time architecture Empty and Full flags signal FIFO status Almost-Empty and Almost-Full flags set to Empty+7 and Full-7, respectively Output enable puts output data bus in high-impedance state Produced with advanced submicron CMOS technology Available in 28-pin 300 mil plastic DIP For surface mount product please see the IDT72421/72201/72211/ 72221/72231/72241 data sheet Industrial temperature range (-40C to +85C) is available
FUNCTIONAL BLOCK DIAGRAM
D0 - D7 WCLK WEN INPUT REGISTER FLAG LOGIC RAM ARRAY 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 EF AE AF FF
WRITE CONTROL LOGIC
WRITE POINTER
READ POINTER
READ CONTROL LOGIC
OUTPUT REGISTER
RESET LOGIC RCLK RS OE Q0 - Q7 REN
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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
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2002 Integrated Device Technology, Inc. All rights reserved. Product subject to change without notice.
SEPTEMBER 2002
DSC-2680/2
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFOTM 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
D4 D3 D2 D1 D0 AF AE GND RCLK REN OE EF FF Q0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D5 D6 D7 RS WEN WCLK VCC Q7 Q6 Q5 Q4 Q3 Q2 Q1
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PLASTIC THIN DIP (P28-2, order code: TP) TOP VIEW
PIN DESCRIPTIONS
Symbol D0 - D7 RS WCLK WEN Q0 - Q7 RCLK REN OE EF AE AF FF VCC GND Name Data Inputs Reset Write Clock Write Enable Data Outputs Read Clock Read Enable Output Enable Empty Flag Almost-Empty Flag Almost-Full Flag Full Flag Power Ground I/O I I I I O I I I O O O O Description Data inputs for a 8-bit bus. When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and AF go HIGH, and AE and EF go LOW. A reset is required before an initial WRITE after power-up. Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when WEN is asserted. When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. Data will not be written into the FIFO if the FF is LOW. Data outputs for a 8-bit bus. Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted. When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. When AE is LOW, the FIFO is almost empty based on the offset Empty+7. AE is synchronized to RCLK. When AF is LOW, the FIFO is almost full based on the offset Full-7. AF is synchronized to WCLK. When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. One +5 volt power supply pin. One 0 volt ground pin.
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IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFOTM 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TSTG IOUT
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Rating Terminal Voltage with Respect to GND Storage Temperature DC Output Current
Com'l & Ind'l -0.5 to +7.0 -55 to +125 -50 to +50
Unit V C mA
RECOMMENDED OPERATING CONDITIONS
Symbol VCC GND VIH VIL TA Parameter Supply Voltage Commercial Supply Voltage Input High Voltage Commercial Input Low Voltage Commercial Operating Temperature Commercial Min. 4.5 0 2.0 -- 0 Typ. Max. 5.0 5.5 0 -- -- -- 0 -- 0.8 70 Unit V V V V C
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V 10%, TA = 0C to +70C) IDT72420 IDT72200 IDT72210 IDT72220 IDT72230 IDT72240 Commercial tCLK = 10, 15, 25 ns Typ. -- -- -- -- -- --
Symbol ILI(1) ILO(2) VOH VOL ICC1(3,4,5) ICC2
(3,6)
Parameter Input Leakage Current (any input) Output Leakage Current Output Logic "1" Voltage, IOH = -2 mA Output Logic "0" Voltage, IOL = 8 mA Active Power Supply Current Standby Current
Min. -1 -10 2.4 -- -- --
Max. 1 10 -- 0.4 40 5
NOTES: 1. Measurements with 0.4 VIN VCC. 2. OE VIH, 0.4 VOUT VCC. 3. Tested with outputs open (IOUT = 0). 4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz. 5. Typical ICC1 = 1.7 + 0.7*fS + 0.02*CL*fS (in mA). These equations are valid under the following conditions: VCC = 5V, TA = 25C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF). 6. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
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IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFOTM 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V 10%, TA = 0C to + 70C)
IDT72420L10 IDT72200L10 IDT72210L10 IDT72220L10 IDT72230L10 IDT72240L10 Min. Max. -- 100 2 10 4.5 4.5 3 0.5 3 0.5 10 8 8 --
(2)
Symbol fS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tRSF tOLZ tOE tOHZ tWFF tREF tAF tAE tSKEW1 tSKEW2
Parameter Clock Cycle Frequency Data Access Time Clock Cycle Time Clock High Time Clock Low Time Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Reset Pulse Width(1) Reset Setup Time Reset Recovery Time Reset to Flag and Output Time Output Enable to Output in Low-Z Output Enable to Output Valid Output Enable to Output in High-Z(2) Write Clock to Full Flag Read Clock to Empty Flag Write Clock to Almost-Full Flag Read Clock to Almost-Empty Flag Skew time between Read Clock & Write Clock for Empty Flag & Full Flag Skew time between Read Clock & Write Clock for Almost-Empty Flag & Almost-Full Flag
Commercial IDT72420L15 IDT72200L15 IDT72210L15 IDT72220L15 IDT72230L15 IDT72240L15 Min. Max. -- 66.7 2 15 6 6 4 1 4 1 15 10 10 -- 0 3 3 -- -- -- -- 6 15 10 -- -- -- -- -- -- -- -- -- -- 15 -- 8 8 10 10 10 10 -- --
IDT72420L25 IDT72200L25 IDT72210L25 IDT72220L25 IDT72230L25 IDT72240L25 Min. Max. -- 40 2 25 10 10 6 1 6 1 15 15 15 -- 0 3 3 -- -- -- -- 10 18 15 -- -- -- -- -- -- -- -- -- -- 25 -- 13 13 15 15 15 15 -- --
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
6.5 -- -- -- -- -- -- -- -- -- -- 10 -- 6 6 6.5 6.5 6.5 6.5 -- --
0 2 2 -- -- -- -- 4 10
NOTES: 1. Pulse widths less than minimum values are not allowed. 2. Values guaranteed by design, not currently tested.
CAPACITANCE (TA = +25C, f = 1.0 MHz)
Symbol CIN
(2) (1, 2)
Parameter Input Capacitance Output Capacitance
Conditions VIN = 0V VOUT = 0V
Max. 10 10
Unit pF pF
D.U.T. 680
5V 1.1K
COUT
NOTES: 1. With output deselected. (OE VIH) 2. Characterized values, not currently tested.
30pF*
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figure 1 4
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or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFOTM 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIAL TEMPERATURE RANGE
SIGNAL DESCRIPTIONS
INPUTS: Data In (D0-D7) -- Data inputs for 8-bit wide data. CONTROLS: RESET (RS) -- Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power up before a write operation can take place. The Full Flag (FF) and Almost-Full Flag (AF) will be reset to HIGH after tRSF. The Empty Flag (EF) and Almost-Empty Flag (AE) will be reset to LOW after tRSF. During reset, the output register is initialized to all zeros. WRITE CLOCK (WCLK) -- A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock (WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH transition of the Write Clock. The Full Flag (FF) and Almost-Full Flag (AF) are synchronized with respect to the LOWto-HIGH transition of the Write Clock. The Write and Read Clocks can be asynchronous or coincident. WRITE ENABLE (WEN) -- When Write Enable (WEN) is LOW, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every Write Clock (WCLK). Data is stored in the RAM array sequentially and independently of any on-going read operation. When Write Enable (WEN) is HIGH, the input register holds the previous data and no new data is allowed to be loaded into the register. To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, the Full Flag (FF) will go HIGH after tWFF, allowing a valid write to begin. Write Enable (WEN) is ignored when the FIFO is full. READ CLOCK (RCLK) -- Data can be read on the outputs on the LOW-toHIGH transition of the Read Clock (RCLK). The Empty Flag (EF) and Almost-Empty flag (AE) are synchronized with respect to the LOW-to-HIGH transition of the Read Clock. The Write and Read Clocks can be asynchronous or coincident. READ ENABLE (REN) -- When Read Enable (REN) is LOW, data is read from the RAM array to the output register on the LOW-to-HIGH transition of the Read Clock (RCLK). When Read Enable (REN) is HIGH, the output register holds the previous data and no new data is allowed to be loaded into the register.
When all the data has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after tREF and a valid read can begin. Read Enable (REN) is ignored when the FIFO is empty. OUTPUT ENABLE (OE) -- When Output Enable (OE) is enabled (LOW), the parallel output buffers receive data from the output register. When Output Enable (OE) is disabled (HIGH), the Q output data bus is in a highimpedance state. OUTPUTS: FULL FLAG (FF) -- The Full Flag (FF) will go LOW, inhibiting further write operation, when the device is full. If no reads are performed after Reset (RS), the Full Flag (FF) will go LOW after 64 writes for the IDT72420, 256 writes for the IDT72200, 512 writes for the IDT72210, 1,024 writes for the IDT72220, 2,048 writes for the IDT72230, and 4,096 writes for the IDT72240. The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH transition of the Write Clock (WCLK). EMPTY FLAG (EF) -- The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating the device is empty. The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH transition of the Read Clock (RCLK). ALMOST-FULL FLAG (AF) -- The Almost-Full Flag (AF) will go LOW when the FIFO reaches the almost-full condition. If no reads are performed after Reset (RS), the Almost-Full Flag (AF) will go LOW after 57 writes for the IDT72420, 249 writes for the IDT72200, 505 writes for the IDT72210, 1,017 writes for the IDT72220, 2,041 writes for the IDT72230 and 4,089 writes for the IDT72240. The Almost-Full Flag (AF) is synchronized with respect to the LOW-toHIGH transition of the Write Clock (WCLK). ALMOST-EMPTY FLAG (AE) -- The Almost-Empty Flag (AE) will go LOW when the FIFO reaches the almost-empty condition. If no reads are performed after Reset (RS), the Almost-Empty Flag (AE) will go HIGH after 8 writes for the IDT72420, IDT72200, IDT72210, IDT72220, IDT72230 and IDT72240. The Almost-Empty Flag (AE) is synchronized with respect to the LOWto-HIGH transition of the Read Clock (RCLK). DATA OUTPUTS (Q0-Q7) -- Data outputs for 8-bit wide data.
TABLE 1 -- STATUS FLAGS
IDT72420 0 1 to 7 8 to 56 57 to 63 64 IDT72200 0 1 to 7 8 to 248 249 to 255 256 Number of Words in FIFO IDT72210 IDT72220 0 1 to 7 8 to 504 505 to 511 512 0 1 to 7 8 to 1,016 1,017 to 1,023 1,024 IDT72230 0 1 to 7 8 to 2,040 2,041 to 2,047 2,048 IDT72240 0 1 to 7 8 to 4,088 4,089 to 4,095 4,096 FF H H H H L AF H H H L L AE L L H H H EF L H H H H
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IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFOTM 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIAL TEMPERATURE RANGE
tRS RS tRSS REN tRSS WEN tRSF EF, AE tRSF FF, AF tRSF Q0 - Q7 OE = 0
NOTES: 1. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1. 2. The Clocks (RCLK, WCLK) can be free-running during reset.
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tRSR
tRSR
OE = 1(1)
Figure 2. Reset Timing
tCLK tCLKH WCLK tDS D0 - D7
DATA IN VALID
tCLKL
tDH
tENS WEN tWFF FF tSKEW1(1) RCLK
tENH NO OPERATION tWFF
REN
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NOTE: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 3. Write Cycle Timing
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IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFOTM 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
tCLK tCLKH RCLK tENS REN tREF EF tA Q0 - Q7 tOLZ tOE tSKEW1 WCLK
(1)
COMMERCIAL TEMPERATURE RANGE
tCLKL
tENH NO OPERATION tREF
VALID DATA tOHZ
OE
WEN
NOTE: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
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Figure 4. Read Cycle Timing
WCLK tDS D0 - D7 tENS WEN tFRL tSKEW1 RCLK tREF EF tENS REN tA Q0 - Q7 tOLZ tOE OE
NOTE: 1. When tSKEW1 minimum specification, tFRL maximum = tCLK + tSKEW1 When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1 The Latency Timing apply only at the Empty Boundary (EF = LOW).
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D0 (first valid write)
D1
D2
D3
(1)
tA D0 D1
Figure 5. First Data Word Latency Timing
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IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFOTM 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
NO WRITE WCLK tSKEW1 D0 - D7 tWFF FF tENS WEN tDS DATA WRITE tWFF tSKEW1 NO WRITE
COMMERCIAL TEMPERATURE RANGE
NO WRITE
tWFF tENS
RCLK tENH tENS REN OE LOW tA tA tENS tENH
Q0 - Q7
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
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Figure 6. Full Flag Timing
WCLK tDS D0 - D7 tENS WEN tFRL tSKEW1 RCLK tREF EF tREF tREF
(1)
tDS DATA WRITE 1 tENH tENS DATA WRITE 2 tENH
(1)
tFRL tSKEW1
REN OE LOW tA Q0 - Q7 DATA IN OUTPUT REGISTER DATA READ
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NOTE: 1. When tSKEW1 minimum specification, tFRL maximum = tCLK + tSKEW1 When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1 The Latency Timing apply only at the Empty Boundary (EF = LOW).
Figure 7. Empty Flag Timing
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IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFOTM 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIAL TEMPERATURE RANGE
tCLKH WCLK
tCLKL (2)
tENS WEN
tENH
tAF
AF
Full - 8 words in FIFO
Full - 7 words in FIFO tSKEW2(1) tAF
RCLK tENS REN tENH
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NOTES: 1. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for AF to change during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then AF may not change state until the next WCLK edge. 2. If a write is performed on this rising edge of the Write Clock, there will be Full - 6 words in the FIFO when AF goes LOW.
Figure 8. Almost Full Flag Timing
tCLKH
tCLKL
WCLK tENS WEN Empty+8 AE Empty+7 tSKEW2 (1) tAE RCLK tENS REN tENH
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tENH
tAE (2)
NOTES: 1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for AE to change during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then AE may not change state until the next RCLK edge. 2. If a read is performed on this rising edge of the Read Clock, there will be Empty - 6 words in the FIFO when AE goes LOW.
Figure 9. Almost Empty Flag Timing
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IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFOTM 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
COMMERCIAL TEMPERATURE RANGE
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION - A single IDT72420/72200/72210/ 72220/72230/72240 may be used when the application requirements are for 64/256/512/1,024/2,048/4,096 words or less. See Figure 10.
RESET (RS)
WRITE CLOCK (WCLK) WRITE ENABLE (WEN) IDT 72420 72200 72210 72220 72230 72240
READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE) DATA OUT (Q0-Q7) EMPTY FLAG (EF) ALMOST-EMPTY(AE)
DATA IN (D0-D7) FULL FLAG (FF) ALMOST-FULL (AF)
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Figure 10. Block Diagram of Single 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 Synchronous FIFO
WIDTH EXPANSION CONFIGURATION - Word width may be increased any one device. Figure 11 demonstrates a 16-bit word width by using two simply by connecting the corresponding input control signals of multiple IDT72420/72200/72210/72220/72230/72240s. Any word width can be devices. A composite flag should be created for each of the endpoint status attained by adding additional IDT72420/72200/72210/72220/72230/72240s. flags (EF and FF) The partial status flags (AE and AF) can be detected from
RESET (RS)
RESET (RS)
DATA IN (D)
16
8
8 READ CLOCK (RCLK)
WRITE CLOCK (WCLK) READ ENABLE (REN) WRITE ENABLE (WEN) OUTPUT ENABLE (OE) ALMOST-FULL (AF) FULL FLAG (FF) #1 FULL FLAG (FF) #2 IDT 72420 72200 72210 72220 72230 72240 IDT 72420 72200 72210 72220 72230 72240 ALMOST-EMPTY (AE) EMPTY FLAG (EF) #1 EMPTY FLAG (EF) #2 8 DATA OUT(Q) 16
8
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Figure 11. Block Diagram of 64 x 16, 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16, 4,096 x 16 Synchronous FIFO Used in a Width Expansion Configuration
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DEPTH EXPANSION The IDT72420/72200/72210/72220/72230/72240 can be adapted to applications when the requirements are for greater than 64/256/512/1,024/ 2,048/4,096 words. Depth expansion is possible by using expansion logic to direct the flow of data. A typical application would have the expansion logic alternate data accesses from one device to the next in a sequential manner.
Please see the Application Note "DEPTH EXPANSION IDT'S SYNCHRONOUS FIFOs USING RING COUNTER APPROACH" for details of this configuration.
ORDERING INFORMATION
IDT XXXXX X XX XX DeviceType Power Speed Package X Process / Temperature Range
BLANK
Commercial (0C to +70C)
TP
Plastic Thin DIP (300 mil, P28-2)
10 15 25 L 72420 72200 72210 72220 72230 72240
NOTE: 1. Industrial temperature range is available by special order.
Commercial
Clock Cycle Time (tCLK) Speed in Nanoseconds
Low Power 64x 8 SyncFIFO 256 x 8 SyncFIFO 512 x 8 SyncFIFO 1,024 x 8 SyncFIFO 2,048 x 8 SyncFIFO 4,098 x 8 SyncFIFO
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DATASHEET DOCUMENT HISTORY
10/03/2000 05/01/2001 pgs. 1, 3, 4 and 11. pgs. 1, 2, 3, 4 and 11.
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
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for Tech Support: 408-330-1753 FIFOhelp@idt.com

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